This invention relates to silicon devices and more particularly to silicon integrated circuits. Typical of such circuits are dynamic random access memories of the kind which utilize an array of memory cells, each of which includes an access or gating transistor for controlling the charging and discharging of a series-connected storage capacitor.
It will be convenient to describe the invention with particular reference to such a dynamic RAM, although the invention in its broader aspects is not limited to such devices.
In memory technology, the emphasis is on increasing the number of memory cells that can be included on a single chip. To this end, it is important to minimize the surface area required of a memory cell since the surface area available on the chip for the memory array currently is a limiting factor in the total number of cells that can be included in one chip. Presently the preferred cell from the standpoint of minimum area is the one-transistor, one-capacitor cell. In such a cell, the capacitor normally has been a surface device and its capacitance is determined by the amount of surface area it is permitted to occupy. A characteristic of dynamic RAMs of this type is that the amount of signal charge that can be stored and later read out is a function of the capacitance of the storage capacitor, and accordingly the larger the capacitance the more easily is the signal detected. Additionally, for a high signal-to-noise ratio it is also important that the storage capacitance be large compared to the parasitic capacitance of the sense lines. For these reasons, it is generally advantageous to have as large a storage capacitance as size considerations permit.
To increase the storage capacitance, there have been proposed in the past memory cells in which the storage capacitor is buried under an access transistor of the V-MOS type to facilitate interconnection, but these cells have proven difficult to fabricate reliably in the densities needed to be competitive with available technology.